The present invention relates to computer graphics system, and more particularly to a method and system for more efficiently using processors of a computer graphics system for processing data for primitives.
A conventional computer graphics system can display graphical images of objects on a display. The display includes a plurality of display elements, known as pixels, typically arranged in a grid. In order to display objects, the conventional computer graphics system typically breaks each object into a plurality of polygons, termed primitives. A conventional system then renders the primitives in a particular order.
Some computer graphics systems are capable of rendering the primitives in raster order. Such as system is described in U.S. Pat. No. 5,963,210, entitled xe2x80x9cGraphics Processor, System and Method for Generating Screen Pixels in Raster Order Utilizing a Single Interpolatorxe2x80x9d and assigned to the assignee of the present application. In such a system, all of the primitives intersecting a particular pixel are rendered for that pixel. The primitives intersecting a next pixel in the line are then rendered. Typically, this process proceeds from left to right in the line until the line has been rendered, then recommences on the next line. The frame is rendered line by line, until the frame has been completed.
In order to render the frame, the primitives are loaded into processors. Typically, all of the primitives starting at a particular line are loaded into the processors at the start of the line. After the line has completed processing, primitives which have expired are ejected. An expired primitive is one which can not be present on the next line. In other words, an expired primitive has a bottom that is no lower than the line that was just processed. Any new primitives for the next line are loaded at the start of the next line. The line is then processed as described above. This procedure continues until the frame is rendered.
Although the system and method function well for there intended purpose and can render primitives in raster order, one of ordinary skill in the art will readily recognize that the system and method have limitations. In particular, the complexity of the frame being rendered is limited by the number of processors available. As described above, all of the primitives for line are provided to processors at the start of a line and ejected at the end of a line. The total number of primitives that can be provided to the processors is limited by the number of processors. Thus, the total number of primitives that can be rendered for a particular line is limited by the number of processors in the system. For similar reasons, the total number of primitives that can overlap at a particular pixel is also limited by the number of processors in the system. Typically, the number of processors is on the order of sixteen or thirty-two. As a result, the number of primitives that overlap at a particular pixel and that can be processed for a line is limited to sixteen or thirty-two. The complexity of the frame is thereby limited. This limitation can be improved by increasing the number of processors. However, increasing the number of processors increases the space consumed by the graphics system, which is undesirable.
Furthermore, the processes of loading primitives and ejecting expired primitives each consume time and resources. In addition, in a complex scene, many primitives might expire at the end of a particular line and a large number of primitives might start at the next line. Ejecting the expired primitives and loading the new primitives might cause a significant delay in the pipeline.
Accordingly, what is needed is a system and method for more efficiently utilizing the processors of a computer graphics system. The present invention addresses such a need.
The present invention provides a method and system for more efficiently utilizing at least one processor and at least one bypass processor of a computer graphics system. The processor(s) include a particular number of processors. In addition, the term bypass processor includes one or more bypass processors. The processor(s) and at least one bypass processor render a plurality of primitives. Each primitive has a left corner, a right corner and a top. The primitives are ordered based on the left corner of each of the plurality of primitives. The method and system include providing a merge circuit, a distributor and a feedback circuit. The merge circuit determines a left edge and a right edge for each of the plurality of primitives. The distributor is coupled with the feedback circuit and outputs a first portion of the plurality of primitives. The distributor provides a second portion of the plurality of primitives to the processor(s) and provides a third portion of the plurality of primitives to the at least one bypass processor if the first portion of the plurality of primitives includes more primitives than the particular number of processors. The second portion of the plurality of primitives includes a number of primitives that is not greater than the particular number of processors. The feedback circuit, which is coupled to the merge circuit and the distributor, re-inputs a fourth portion of the plurality of primitives to the at least one bypass processor until the first portion of the plurality of primitives has been rendered for a particular line. The controller controls the feedback circuit, the distributor and the merge circuit.
According to the system and method disclosed herein, the present invention provides a more efficient mechanism for utilizing the processors.